BCM56990 · 25.6 Tbps · 64×400G

Broadcom Tomahawk 4 Tomahawk 4 Switch 25.6 Tbps · 64 × 400G · the cost-efficient 400G generation.

One open platform qualified on OcNOS-DC: Edgecore AS9736-64D. Tomahawk 4 is the cost-efficient 400G tier: 25.6 Tbps across 64×400G ports, below the TH5 800G spine, with 400G economics.

01The Switch 02Inside the Silicon 03Generation Jump 04OcNOS-DC
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25.6Tbps
Switch Capacity
64×400G
Native Port Radix
~114MB
Shared Buffer
2RU
Form Factor
50GPAM4
SerDes Per Lane
01
The Switch

One platform. One purpose: cost-efficient 400G.

Edgecore AS9736-64D: a 2RU 64×400G QSFP56-DD switch on the BCM56990 Tomahawk 4. It ships with ONIE pre-loaded and runs the same OcNOS-DC software as the TH5 spines and TD4 leaves. One qualified platform: the 64×400G tier of the OcNOS-DC portfolio, below the TH5 800G spine.

Edgecore· DCS520 platform family
400G AI fabric · DCI

AS9736-64D

Qualified on OcNOS-DC · ONIE pre-loaded
Ports
64 × QSFP56-DD (400G)Breakout: 2×200 / 4×100 / 2×50 (up to 256 logical ports)
Form
2RU · 21.5 kg
Power
2100 W max · hot-swap redundant 2400 W AC/HVDC PSUs24 W per transceiver on 16 ports, 13 W on the other 48
CPU
Intel Xeon D-class · 32 GB RAM
▌ Pick this when

400G AI fabric for single-pod GPU clusters on 400G NICs, and 400G aggregation / DCI roles, where 25.6T of 64×400G at merchant-silicon cost does the job without paying for 800G ports.

Edgecore AS9736-64D datasheet PDF

Tomahawk 4: 64 × 400G

Pick when 400G NICs anchor the cluster and cost-per-port matters: 25.6 Tbps of 64×400G, below the price of 800G silicon.

You are here · 25.6 Tbps

Tomahawk 5: 64 × 800G

Pick when the cluster needs 800G ports natively, or 800G per port at the same 64-port radix is worth the per-port premium. Tomahawk 5 page →

Step up · 51.2 Tbps

Trident 4: DC leaf

Pick when the role is DC leaf at 100G/400G with smaller capacity envelope. Different chip family, same OcNOS-DC software, lower cost per port. (Trident 4 page coming.)

Smaller box · 12.8 Tbps
02
Inside the Silicon

Tomahawk 4: the cost-efficient 25.6T switch chip.

Tomahawk 4 (BCM56990) is a 25.6 Tbps switch with a 64×400G native radix. It uses an integrated shared buffer of about 114 MB, tuned for lossless RoCEv2. This low-latency switch chip is not a deep-buffer router chip: use a Jericho or Qumran StrataDNX part for GB-scale buffering. For a 400G AI or DC fabric, the shared buffer and DLB fit the job.

Why that matters: lossless RoCEv2 relies on PFC and ECN marking to keep queues shallow, DCQCN rate control on the NICs, and DLB to spread elephant flows so no single queue builds up. TH4 runs PFC, ECN marking, and DLB in the ASIC at 400G.

SeriesStrataXGS BufferOn-die shared Load balancingDLB
Broadcom Tomahawk 4 (BCM56990) port radix shown as a grid of 64 ports, each 400G, totaling 25.6 Tbps
What 64 x 400G looks like: 512 lanes of 50G PAM4 totaling 25.6 Tbps on the BCM56990 die.

Why TH4 stays in the AI fabric conversation even after TH5 ships.

400G at merchant-silicon economics, on the same OcNOS-DC software as the 800G TH5.

PRINCIPLE 01 · WHY TH4

400G at a lower cost per port than 800G silicon.

TH4 provides 25.6 Tbps across 64×400G ports. For clusters with 400G GPU NICs, it delivers an OcNOS-DC lossless fabric at a lower price than 800G TH5 silicon, with half the per-port bandwidth.

64×400G · cost-optimized
PRINCIPLE 02

50G PAM4 SerDes: 512 lanes.

TH4 runs 512 lanes of 50G PAM4 for 25.6T. Eight lanes per QSFP56-DD port gives 400G native; breakout extends to 200G/100G/50G for mixed-speed deployments.

512 lanes · 50G PAM4
PRINCIPLE 03

Hardware dynamic load balancing.

Flowlet-aware load balancing in the ASIC, with no controller round-trip. OcNOS-DC enables this as Dynamic Load Balancing (DLB), spreading elephant flows across the fabric so no single queue builds up under RoCEv2 collective traffic.

DLB · flowlet rebinding
PRINCIPLE 04

Mature silicon.

Predictable behaviour and a known thermal envelope make this a natural choice for a brownfield TH3 fabric refresh.

Same OcNOS-DC as TH3
03
Generation Jump

Twice the capacity and radix on the same OcNOS-DC software.

TH3 (12.8 Tbps · 32×400G) is the previous 400G generation. TH4 doubled the capacity and the port radix, at 400G economics.

Switching capacity
12.8 Tbps → 25.6 Tbps

Doubled capacity in a 2RU box.

Native port radix
32 × 400G → 64 × 400G

Twice the ports at the same speed: fits Clos designs without an extra tier.

100G breakout ports
128 × 100G → 256 × 100G

Each 400G port splits into 4 × 100G on both platforms.

Network OS
OcNOS-DC → OcNOS-DC

Both platforms run OcNOS-DC, so a refresh keeps the same operations model.

The next jump: TH5 doubles again to 51.2 Tbps and 64 × 800G. TH4 stays the cost-efficient 400G tier for clusters that don't need 800G ports yet. Tomahawk 5 page →
04
What OcNOS-DC Ships

Same software as the TH5 spine.

The same OcNOS-DC software runs across TH3, TH4, and TH5 platforms, with lossless RoCEv2 (PFC + ECN) and streaming telemetry on each.

PFC + ECN, and the shared buffer absorbs the rest.

Standard PFC, ETS, and ECN. DLB spreads elephant flows to keep queues shallow, while PFC deadlock detection and recovery clears pause deadlocks.

DLB rebinds flowlets in the ASIC.

OcNOS-DC Dynamic Load Balancing (DLB) on TH4 uses flowlet rebinding to resolve ECMP hash collisions in the ASIC, without a controller round-trip.

Per-port, per-priority. Auto-drain.

Detects paused-queue cycles before they hang training jobs, and drains them automatically so a PFC pause storm can't stall a collective.

PFC Deadlock Recovery

Telemetry on the wire.

gNMI streaming telemetry, dial-in and dial-out, with an on-change stream mode, so congestion is visible, not a black box.

BGP · OSPF · IS-IS, plus EVPN-VXLAN where supported.

Layer 3 routing with BGP, OSPF, and IS-IS runs on the same silicon. The TH4 spine also supports routing, so you can operate it like the rest of your network.

Same OcNOS-DC software as TH5: every feature lights up where the silicon supports it.

Layer 3 routing · L1/L2 · AI fabric primitives · Multicast · QoS · Security · Hardware · Management. Per-platform qualification visible on the public matrix.

RoCEv2 / PFC ECN DLB BGP / OSPF / IS-IS gNMI / NETCONF ZTP buffer tuning
Day-0 to Day-2

ZTP. gNMI on-change. NETCONF + YANG. DCBX.

Bring up the AS9736-64D in the rack with zero-touch provisioning. Stream gNMI telemetry with dial-in or dial-out to your observability stack, and tune thresholds through YANG-modelled configuration.

ZTP IPv4/IPv6 gNMI NETCONF OpenConfig YANG DCBX LLDP Ansible

Three operator profiles. One silicon for all three.

The 64×400G radix at 400G economics puts AS9736-64D in three different conversations: AI fabric, DCI, and brownfield refresh. Same switch, different framing of the same architectural question.

400G NIC fabric without paying for 800G silicon.

"Our cluster is on 400G NICs. We don't need 800G ports yet, and we're not paying the 800G premium for ports we can't use."

TH4 spines on AS9736-64D support lossless RoCEv2 and DLB rebinding. Use a three-tier Clos for multi-pod scale-out, with the same OcNOS-DC software as the adjacent TH5 deployment.

DC · 400G Spine

400G DCI transport without a chassis-router bill.

"Our cross-DC links need 400G aggregation and EVPN transport at a reasonable price. Chassis routers cost far more than we expect to pay."

64×400G at merchant-silicon cost, a full L3 stack, gNMI telemetry, and EVPN-VXLAN inter-DC where the platform supports it. Open hardware for 400G DCI transport without the 800G price. For designs that must absorb sustained deep-buffer congestion, use a StrataDNX Jericho platform instead of TH4.

DC · DCI · Aggregation

Doubled capacity, same operations model.

"We have a TH3 fabric in production. We need more capacity, but we don't want to redesign the NOS layer or retrain the network team."

Same OcNOS-DC software runs on TH3 and TH4. Brownfield refresh keeps configs, automation, and gNMI pipelines intact. Capacity doubles and the operating model stays the same.

DC · Refresh
Full Feature Matrix AI Fabric Solution Reference Topologies Hardware Compatibility List

Questions architects ask

One platform: the Edgecore AS9736-64D, a 2RU 64×400G QSFP56-DD switch built on the Broadcom BCM56990 (Tomahawk 4, 25.6 Tbps). Ships ONIE pre-loaded, runs the same OcNOS-DC software as the TH5 spines and the TD4 leaves. It is the 64×400G platform in the OcNOS-DC portfolio.
Cost: at single-pod scale with 400G GPU NICs, a TH4 fabric costs less per port than TH5. It provides 25.6 Tbps across 64×400G ports on a low-latency, shared-buffer switch chip. A three-tier Clos still fits. Step up to TH5 (800G) only when 800G ports are on the BoM or when you want to halve spine-leaf cabling for the same aggregate bandwidth.
Tomahawk 4 is a shared-buffer, low-latency switch chip, not a deep-buffer router chip. Its integrated packet buffer is about 114 MB, sized for lossless RoCEv2 with PFC and ECN. For GB-scale deep buffering (long-haul DCI hold or heavy N:1 fan-in), use a Jericho or Qumran StrataDNX router chip. For a low-latency 400G AI or DC fabric, the TH4 shared buffer and DLB fit the job.
Choose TH5 (AIS800-64D) when 800G ports are on the BoM or when you want 800G per port at the same 64-port radix, which halves the spine-leaf cabling for the same aggregate bandwidth. Choose TH4 (AS9736-64D) when 400G NICs anchor the cluster and the per-port budget rules out 800G silicon. Both run the same OcNOS-DC software.
Yes. TH4 supports flowlet-aware load-balancing in the ASIC, with no controller round-trip. OcNOS-DC turns this on as Dynamic Load Balancing (DLB), so a TH4 fabric resolves elephant-flow hash collisions in hardware. PFC deadlock detection & recovery and ETS are also available.
Capacity doubled twice (12.8 → 25.6 → 51.2 Tbps). The native radix went from 32 × 400G (TH3) to 64 × 400G (TH4) to 64 × 800G (TH5). OcNOS-DC supports all three with the same software: brownfield refresh keeps configs and gNMI pipelines intact.
The 64×400G radix is more than a sub-1 Tbps SP edge or cell-site gateway needs; choose Qumran (Q2A/Q2U/Q2C) for those roles. For a DC leaf at 100G/400G with a smaller capacity envelope, choose Trident 4 (TD4) at 12.8 Tbps. If the cluster needs 800G ports today, TH4 requires an extra Clos tier, so choose TH5. TH4 is the right fit where 400G is enough and cost per port matters.

Designing a 400G fabric? Let's size it together.

30-minute architecture session with an OcNOS network architect. Bring your GPU count, NIC speed, and burst-pattern expectations, and leave with a sized BoM around AS9736-64D and a placement plan vs the TH5 / TD4 alternatives.

Book an Architecture Review Test Drive OcNOS-DC

Go deeper. Take it with you.

The product datasheet plus short, technical downloads that go further than this page.

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