Network engineers picking a Tomahawk 5 switch — start here. Edgecore AIS800-64D and AS9817-64D, UfiSpace S9321-64E and S9321-64EO. Same silicon, same OcNOS-DC image, four procurement paths. Specs, decision rules, and the OcNOS-DC feature surface — without the marketing fluff.
Two hardware designs, four SKUs. All four ship ONIE pre-loaded and run the same OcNOS-DC image — the differences are form factor (QSFP-DD vs OSFP), branding (AI-fabric SKU vs general-DC SKU), and which optics ecosystem the deployment is built around. Each card links to the full vendor datasheet (PDF, hosted locally).
GPU-cluster AI fabric. AI-branded SKU of the DCS560 — same hardware as AS9817-64D under different framing.
General data-center fabric or DCI duty. Same DCS560 chassis as AIS800-64D, branded for non-AI workloads.
Large, low-entropy AI/ML flows. UfiSpace markets the 64E for AllReduce-dominant traffic where TH5 adaptive routing is the design centre.
800G ZR/ZR+ coherent or other higher-power module classes. OSFP form factor of the 64E — pick when the optics drive the cage choice.
The BCM78900 is a single 5 nm monolithic die delivering 51.2 Tbps of switching capacity — feeding 64 ports of 800GbE, 128 of 400G, or 256 of 200G natively. It was Broadcom's first 5 nm merchant switch IC and the first product anywhere to support 800GbE at the cage. 512 SerDes lanes running 100G PAM4 — the same lane count as Tomahawk 4, twice the per-lane speed.
Beyond raw capacity, three architectural choices made TH5 the silicon under most production AI fabrics: a shared-buffer architecture that absorbs NCCL micro-bursts, hardware Cognitive Routing (DLB) that rebinds elephant flows in the ASIC, and 5 nm thermal headroom that lets 30 W QSFP-DD800 cages run without per-port active cooling.
Specs verifiable against Broadcom's public BCM78900 product page.
The headline number gets the press. These four engineering choices are what AI fabric architects actually care about.
TH5 carries the same 512 SerDes lanes as TH4 — running them at 100G PAM4 instead of 50G. The throughput double came from speeding up existing infrastructure, not adding to it.
100G PAM4 · 106 GbpsPacket memory pools across all 64 ports — not split per-port. NCCL AllReduce micro-bursts on one port absorb into the fabric-wide pool instead of triggering tail-drop. The single-line reason TH5 wins on RoCEv2.
Shared-buffer · RDMA-tunedBroadcom Cognitive Routing detects congested paths and rebinds elephant flows in the ASIC — no controller round-trip, no ECMP rehashing. OcNOS-DC turns it on as DLB Reactive-Path Rebalance.
DLB · 64 µs flowletThe first 5 nm merchant switch IC. The process shrink is what made 30 W per QSFP-DD800 cage feasible without active per-port cooling — including high-power 800G optics and 8×100G breakout.
TSMC N5 · 30 W/portHonest framing: TH4 (25.6 Tbps · 32×400G · 7 nm) is still excellent for clusters built around 400G NICs. TH5 earns its rack space when 800G radix and AI-fabric primitives both matter.
Doubled at the same rack footprint. Same 2RU, same power envelope class.
Three-tier Clos at 16k GPU instead of four — radix collapses a layer.
First 5 nm merchant switch IC. Thermal headroom for 30 W/port without active cooling.
Same 512 lanes, twice the speed. The throughput double came from existing infrastructure.
Tomahawk 5 has the hardware. The job of the NOS is to expose it — to operators, to telemetry pipelines, to the cluster scheduler — without forcing them to write CLI gymnastics around it. OcNOS-DC ships these primitives as first-class configurable objects with YANG-modelled state.
OcNOS-DC ships PFC + ETS + Dynamic ECN pre-tuned to NCCL collective patterns. Tail latency stays bounded under AllReduce micro-bursts that take community NOS fabrics down. The TH5 shared-buffer pool absorbs synchronised many-to-one traffic that would tail-drop on partitioned-buffer chips.
ECMP hash-collision under elephant flows is the AI fabric killer. OcNOS-DC turns on TH5 Cognitive Routing's flowlet rebinding so AllReduce traffic spreads across every spine path automatically.
Detects paused-queue cycles before they hang training jobs. Auto-recovers without operator intervention.
Buffer depth, ECN marks, PFC pause counts — every threshold a knob, every counter a sensor path. Plugs into Prometheus, Grafana, OTel.
The TH5 spine is also a real router. Full carrier-grade Layer 3 stack on the same silicon — operate the AI fabric like the rest of your network, not like a black box.
Layer 3 routing · L1/L2 · AI/ML fabric primitives · Multicast · QoS · Security · Hardware · Management. Every entry verifiable per-platform on the public matrix.
Bring up a TH5 spine in the rack with zero-touch provisioning. Stream every counter to your observability stack. Tune every threshold via YANG-modelled config. No glue scripts.
Same TH5 die, same OcNOS-DC image, three different framings of the same architectural question: how do you scale lossless east-west without locking the whole stack to one vendor?
"We need 800G to the leaf, lossless RoCEv2, and tail latency that doesn't blow up under AllReduce. Single-vendor lock-in is not on the table."
TH5 64×800G spines, RoCEv2 with NCCL-tuned DCQCN, sub-millisecond DLB rebinding, PFC deadlock watchdog. Three-tier Clos at 16k GPU instead of four — the radix collapses a layer.
DC · AI Fabric SKU"Our customers pick the GPU. We can't tie our fabric BoM to their NIC choice. We need a switch we can buy from two vendors at minimum."
Four OcNOS-validated TH5 SKUs across two vendors (Edgecore, UfiSpace). VRF-Lite tenant isolation, gNMI per-tenant telemetry, EVPN-VXLAN segmentation. One NOS image, multi-vendor hardware.
DC · Multi-Tenant"We have a TH4 fabric in production. The next training cluster needs 800G NICs. We don't want to redesign the whole NOS layer to upgrade the silicon."
Same OcNOS-DC image runs on TH3, TH4, and TH5 platforms. Brownfield refresh keeps configs, automation, and gNMI pipelines intact. UEC 1.0 fabric profile already aligned for the next NIC generation.
DC · UEC-Ready30-minute architecture session with an OcNOS network architect. Bring your GPU count, NIC speed, and tier preference — leave with a sized BoM across all four TH5 SKUs.