BCM88850 · Carrier-core · Internet-scale FIB · 400G ZR ready

Broadcom Jericho 2C+ Jericho 2C+ Routers Carrier-core class. 7.2 / 14.4 Tbps. Pizza-box that replaces a chassis.

Two open-hardware 2RU carrier-core routers validated on OcNOS-SP — Edgecore AS9947-36XKB (single-chip 7.2 Tbps) and UfiSpace S9610-36D (dual-chip 14.4 Tbps). Internet-scale FIB, full IP/MPLS service plane, 400G ZR coherent on every QSFP-DD port.

01The Routers 02Inside the Silicon 03Family Map 04OcNOS-SP
Architektur-Review vereinbaren Test Drive OcNOS VM
7.2/14.4Tbps
Single / Dual Chip
36×400G
All ZR-Ready (S9610)
~1.2M
Internet FIB Capacity
2SKUs
OcNOS-SP Validated
2RU
Pizza-Box Form Factor
01
The Routers
Open hardware running Jericho 2C+

Single-chip and dual-chip. Tier-2 backbone and Tier-1 super-spine.

Two fundamentally different platforms — one BCM88850 die or two — covering the carrier-core capacity envelope from 7.2 to 14.4 Tbps. Both run the same OcNOS-SP image; the chip count is an engineering choice, not an operational one. Each card links to the full vendor datasheet (PDF, hosted locally).

Edgecore· AS9947 series · single-chip
Carrier core · single-chip 7.2 Tbps

AS9947-36XKB

Validated on OcNOS-SP · ONIE pre-loaded
Ports
24 × 100G QSFP28 + 12 × 400G QSFP-DD + 4 × 10G SFP+Breakout: 400G ports break out to 4×100G or 2×200G
Form
2RU · 440 × 649 × 88 mm
Power
~800 W typical · AC/DC redundantFeatures: Class C/D PTP · SyncE · MACsec · 400G ZR ready
CPU/RAM
Intel · 8 GB RAM · deep TCAM
▌ Pick this when

Single-chip carrier core for tier-2 SP backbone, regional ISP, or NSP edge. 7.2 Tbps with full Internet FIB (multi-million BGP routes), 12 × 400G QSFP-DD coherent-ready uplinks, and 24 × 100G drops. The 4 × 10G ports hang off small management/legacy circuits.

Edgecore AS9947-36XKB datasheet PDF
UfiSpace· S9610 series · dual-chip
Carrier core · dual-chip 14.4 Tbps

S9610-36D

Validated on OcNOS-SP · ONIE pre-loaded
Ports
36 × 400G QSFP-DDBreakout: 4×100G or 2×200G or native 400G — every port
Form
2RU · 436 × 762 × 88 mm
Power
~1000 W typical · AC/DC redundantFeatures: Class C/D PTP · SyncE · MACsec · 400G ZR on every port
CPU/RAM
Intel · 16 GB RAM · deep TCAM
▌ Pick this when

Dual-chip carrier core for Tier-1 backbone, IXP edge, or DCI super-spine. 14.4 Tbps with 36 × 400G QSFP-DD — every port coherent-ready. Dual-chip architecture means two J2C+ dies share the workload internally. Deeper deployment than the single-chip AS9947.

UfiSpace S9610-36D datasheet PDF

· Single-chip vs dual-chip — pick by the role

Single (AS9947)7.2 Tbps · simpler internal architecture · predictable latency · sized for tier-2 SP backbone, regional ISP, NSP edge.
Dual (S9610)14.4 Tbps · two BCM88850 dies sharing the workload · sized for Tier-1 backbone, IXP edge, DCI super-spine.
Port mixAS9947 has mixed 100G/400G + 4×10G management. S9610 is 36 × 400G — every port coherent-ready.
FIB scaleBoth cover full Internet table (~1.2M routes) plus headroom for L3VPN VRFs and RPKI ROAs. Same OcNOS-SP image.
02
Inside the Silicon
Carrier-core merchant silicon

Jericho 2C+ — the open-hardware answer to chassis routers.

The BCM88850 Jericho 2C+ is Broadcom's flagship StrataDNX merchant routing silicon — purpose-built for carrier core / IP backbone / DCI super-spine roles. Where Tomahawk and Trident are tuned for DC east-west and SP edge respectively, J2C+ is the chip Broadcom designed for the Internet routing role: deep TCAM for ~1.2M FIB entries, on-chip and HBM-class buffer for asymmetric burst absorption, full IP/MPLS service plane in hardware.

Single-chip platforms (AS9947-36XKB) integrate one BCM88850 die in 7.2 Tbps configuration. Dual-chip platforms (S9610-36D) integrate two dies in 14.4 Tbps configuration with internal cross-connects — effectively a chassis-style architecture in a 2RU pizza box. The OcNOS-SP image abstracts the chip count.

Cross-checked against Broadcom\'s BCM88850 product page and the linked vendor datasheets.

SeriesStrataDNX FIB~1.2M routes · deep TCAM BufferDeep · HBM-class Timing1588v2 Class C/D Optics400G ZR every port

· FIB and capacity at a glance

IPv4 FIB~1.0M routes
IPv6 FIB~250k routes
MPLS labels~256k
L3VPN VRFs~16k
BCM88850 die7.2 Tbps
Single-chip = 7.2 Tbps · dual-chip = 14.4 Tbps. FIB scaled per chip; dual-chip platforms double the table headroom.
Four design choices that matter

Why J2C+ replaces chassis routers in the right roles.

These four architectural choices are what move J2C+ from "merchant-silicon edge" to "merchant-silicon core."

PRINCIPLE 01 · UNIQUE

Internet-scale FIB.

Deep TCAM sized for ~1.2M FIB entries — the full Internet routing table at today\'s scale, with growth headroom for the next half-decade. Plus L3VPN VPNv4/v6 routes, MPLS labels, RPKI ROAs. The smaller Q-family chips can\'t carry full transit; J2C+ can.

~1.2M FIB · deep TCAM
PRINCIPLE 02

Deep buffer for transit.

HBM-class buffer absorbs the asymmetric bursts seen at IXP and transit interconnect — long-lived TCP flows, BGP UPDATE storms, mass-withdraw convergence cascades. Carrier-grade SLAs hold under realistic Internet load.

Deep buffer · HBM-class
PRINCIPLE 03

Single or dual configuration.

One BCM88850 in a 2RU box gives 7.2 Tbps. Two BCM88850 dies in the same 2RU give 14.4 Tbps — internal cross-connects, internal scheduling. The chassis-style architecture in pizza-box form.

Single 7.2T · dual 14.4T
PRINCIPLE 04

400G ZR on every port.

QSFP-DD cages with full ~25 W power budget for OIF/CMIS-compliant 400G ZR and OpenZR+ pluggable coherent. On S9610-36D, all 36 ports are coherent-ready — build a transponder-free DWDM ring out of nothing but routers.

400G ZR · OIF/CMIS
03
The Family Map
Q-family + J-family · end-to-end SP silicon

From cell-site to carrier core. One OcNOS-SP image.

A complete SP architecture on Broadcom merchant silicon — Q2U at the access edge, Q2A in metro aggregation, J2C+ in regional/national core. The NOS layer doesn\'t change.

QUMRAN 2U · BCM88280

Compact SP CSR · access edge.

~360 Gbps. Cell-site / FTTx pre-aggregation / Tier-3 metro. Q2U page →

~360 Gbps · 1RU
QUMRAN 2A · BCM88483

SP edge with deep buffer + 400G ZR.

800 Gbps. Metro aggregation, Tier-2 hub, deep-buffer backbone leaf. Q2A page →

800 Gbps · 1RU
QUMRAN 2C · BCM88480

Larger metro hub.

2 Tbps. Higher port density for tier-2 metro/regional roles. Same Q-family DNA.

2.0 Tbps · 1RU
JERICHO 2C+ · BCM88850

Carrier-core router.

You are here. 7.2/14.4 Tbps with full Internet FIB. Tier-1/Tier-2 backbone, IXP, DCI super-spine.

7.2–14.4 Tbps · 2RU
04
What OcNOS-SP Ships
OcNOS-SP on this silicon

Carrier-grade NOS, sized for Internet-scale routing.

OcNOS-SP exposes J2C+\'s full carrier-core feature surface — Internet-scale FIB, MPLS service plane, IEEE 1588v2 timing, MACsec, 400G ZR coherent — through one configuration model. 800+ features in the OcNOS-SP feature matrix.

Internet-Scale BGP

Full transit table + L3VPN.

Multi-million IPv4/IPv6 routes with BGP-LU, BMP telemetry, RPKI ROV, AS-set / AS-confederation, GR/LLGR. Full L3VPN VPNv4/v6 service plane. Add-path multipath. The features Tier-1 carriers actually deploy — and the table sizes they actually carry.

SR-MPLS · TI-LFA

Segment Routing native, Flex-Algo.

SR-MPLS with TI-LFA fast reroute, Flex-Algorithm constraint paths, RSVP-TE for legacy interop. EVPN-MPLS overlays for multi-tenant L2/L3VPN.

PTP / SyncE

Class C/D timing in the core.

Hardware PTP everywhere — even at the carrier core. Distribute timing to the metro and access tiers from one source.

400G ZR Coherent

iPo-DWDM at the core.

Every QSFP-DD port hosts 400G ZR / OpenZR+. Build transponder-free regional DWDM rings out of routers.

MACsec

Line-rate AES-GCM 256.

Inter-PoP encryption mandatory for many SP fabrics. Hitless rekey on 400G transport.

Validated feature surface

800+ features across the OcNOS-SP matrix.

Same image runs on the cell-site Q2U, the metro Q2A, and the carrier-core J2C+. One configuration model, one automation surface, one operational team — across the entire SP fabric.

BGP · BGP-LU · RPKI SR-MPLS / TI-LFA EVPN-MPLS · L3VPN PTP G.8275.1/2 SyncE G.8262 MACsec 400G ZR / ZR+ RSVP-TE gNMI / NETCONF
Day-0 to Day-2

ZTP. gNMI. NETCONF. FIB telemetry.

Bring up a J2C+ in the rack with zero-touch provisioning. Stream FIB occupancy, BGP route counts, optical-layer state, PTP phase error — all through gNMI. The carrier core becomes observable like the rest of your fabric.

ZTP IPv4/IPv6 gNMI NETCONF OpenConfig YANG BMP telemetry Ansible
Who builds this stack

Three core profiles. One carrier-core silicon.

J2C+ appears in Tier-1, Tier-2, and IXP architectures — each leveraging different sides of the same chip.

Tier-2 SP · Regional Backbone

Replace the chassis with pizza-boxes.

"Our regional backbone runs on legacy chassis routers nearing EOL. We carry full Internet table plus L3VPN. The next refresh shouldn\'t cost $500k per box."

AS9947-36XKB at 7.2 Tbps with single-chip simplicity. Full ~1.2M FIB. SR-MPLS native, EVPN-MPLS for tenant services, MACsec inter-PoP. Same OcNOS-SP image as the metro-aggregation Q2A two boxes downstream.

SP · Tier-2 Backbone
Tier-1 · National Backbone

Dual-chip super-spine in 2RU.

"Our national backbone needs 14 Tbps per node. Chassis routers fit — but we want pizza-box density and faster refresh cycles."

S9610-36D at 14.4 Tbps with dual-chip architecture. 36 × 400G all coherent-ready. Same OcNOS-SP feature surface as the single-chip cousin. Stack two for full N+1 redundancy in 4RU.

SP · Tier-1 Super-Spine
IXP / DCI

Internet exchange or super-spine.

"Our IXP needs to peer with hundreds of ASNs at 100G/400G. Burst patterns are pathological. Chassis architecture is correct but expensive."

Either single or dual J2C+, depending on per-node capacity needs. Deep buffer absorbs IXP burst traffic. Internet FIB carries every peer\'s prefix advertisement. 400G coherent for inter-IXP DCI.

SP · IXP / DCI
Full Feature Matrix SP Networks Solution SR-MPLS Deep-Dive Coherent DCI Deep-Dive Hardware Compatibility List
Frequently Asked

The questions carrier-core architects ask.

Two open-hardware platforms with fundamentally different chip architectures: Edgecore AS9947-36XKB (single BCM88850, 7.2 Tbps, 24 × 100G + 12 × 400G + 4 × 10G) and UfiSpace S9610-36D (dual BCM88850, 14.4 Tbps, 36 × 400G). Both run OcNOS-SP — the same image, the same configuration model. Pick by the capacity tier and port mix the role demands.
A single-chip J2C+ (AS9947-36XKB) is one BCM88850 die with all forwarding inside one ASIC. Predictable latency, simpler internal architecture, smaller power/cost envelope. A dual-chip J2C+ (S9610-36D) has two dies in one chassis with internal cross-connects — twice the capacity and forwarding parallelism, but more complex internal traffic patterns. The OcNOS-SP image abstracts the difference; you don't configure differently. Pick single-chip for tier-2 SP backbone or regional ISP. Pick dual-chip for Tier-1 backbone, IXP edge, or DCI super-spine where 14.4 Tbps in 2RU is the constraint.
BCM88850 has external memory (HBM-class) for forwarding tables — supporting multi-million BGP route entries, large MPLS label tables, and the deep TCAM needed for full Internet routing tables (currently ~1M IPv4 + ~250k IPv6 = ~1.25M routes, growing). Plus headroom for large L3VPN VRF deployments, RPKI ROAs, and PIM multicast state. The smaller Q-family chips have smaller FIB capacities — fine for SP edge, insufficient for full BGP transit at the core.
For many tier-2 / regional roles — yes. A 2RU pizza-box J2C+ at 7.2–14.4 Tbps, with full Internet FIB, MPLS service plane, IEEE 1588 timing, and 400G ZR coherent — covers what mid-range chassis routers handled five years ago, at substantially lower CapEx/OpEx. For Tier-1 internet backbones with 100+ Tbps demand and N+1 redundancy at the line-card level, a chassis router is still the right answer. For everything below that — pizza-box J2C+ is competitive, and the dual-chip S9610-36D scales the envelope further.
Yes — every QSFP-DD port on both validated platforms has the cage power budget for OIF/CMIS-compliant 400G ZR and OpenZR+ pluggable coherent optics. On AS9947-36XKB, the 12 × 400G ports cover this. On S9610-36D, all 36 × 400G ports are coherent-ready — meaning you can build a transponder-free metro/regional DWDM ring out of nothing but routers. EVPN inter-DC stretches the L2/L3 fabric across the optical span.
Different role, different scale. Q2U (BCM88280) is the access edge — ~360 Gbps, cell-site / Tier-3 metro. Q2A (BCM88483) is the metro aggregation — 800 Gbps with deep buffer + timing. Q2C (BCM88480) is larger metro hub — 2 Tbps with more port density. J2C+ (BCM88850) is carrier-core — 7.2/14.4 Tbps with full Internet FIB. In a typical SP architecture: Q2U at the edge, Q2A in metro aggregation, Q2C / J2C+ in regional/national core. Same OcNOS-SP image runs on all of them.
For SP edge or cell-site (Q2U is much cheaper). For metro aggregation (Q2A is right-sized). For DC fabric (no DC-class shared-buffer or RoCEv2 — Trident or Tomahawk). For 800G uplinks (J2C+ doesn't do 800G — TH5 is the silicon for that). J2C+'s sweet spot is "carrier-grade core/super-spine where Internet-scale FIB, deep buffer, and 400G coherent matter together."

Replacing a chassis router with merchant-silicon pizza-boxes?

30-minute architecture session with an OcNOS network architect. Bring your FIB-scale, capacity, and timing requirements — leave with a sized BoM around AS9947-36XKB / S9610-36D.

Architektur-Review vereinbaren Test Drive OcNOS-SP